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e) The host shall negate – CS0, -CS1, A2, A1, and A0. The host shall keep – CS0, -CS1, A2, A1, and A0 negated
until after negating – DMACK at the end of the burst.
f)
Steps I, (d), and (e) shall have occurred at least t ACK before the host asserts – DMACK. The host shall keep –
DMACK asserted until the end of an Ultra DMA burst.
g) The device may negate – DDMARDY t ZIORDY after the host has asserted – DMACK. Once the device has negated
– DDMARDY, the device shall not release – DDMARDY until after the host has negated DMACK at the end of
an Ultra DMA burst.
h) The host shall negate STOP within t ENV after asserting – DMACK. The host shall not assert STOP until after the
first negation of HSTROBE.
i)
j)
The device shall assert – DDMARDY within t LI after the host has negated STOP. After asserting DMARQ and –
DDMARDY the device shall not negate either signal until after the first negation of HSTROBE by the host.
The host shall drive the first word of the data transfer onto D[15:0]. This step may occur any time during
Ultra DMA burst initiation.
k) To transfer the first word of data: the host shall negate HSTROBE no sooner than t UI after the device has
asserted – DDMARDY. The host shall negate HSTROBE no sooner than t DVS after the driving the first word of
data onto D[15:0].
Figure 15: Ultra DMA Data-Out Burst Initiation Timing
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are not in effect until DMARQ and DMACK
are asserted.
6.5.4.4.7 Sustaining an Ultra DMA Data-Out Burst
An Ultra DMA Data-Out burst is sustained by following the steps lettered below. The timing diagram is shown in
Figure 16: Sustained Ultra DMA Data-Out Burst Timing. The associated timing parameters are specified in Table 26:
Ultra DMA Data Burst Timing Requirements and are described in Table 27: Ultra DMA Data Burst Timing
Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The host shall drive a data word onto D[15:0].
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 36 of 102
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